1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device for simultaneously achieving high reliability to laser light radiation and small occupation region and method of manufacturing it.
2. Description of the Related Art
This type of semiconductor device is provided in, for example, a power source wire to supply a power source to a circuit. The semiconductor device is used when the supply of the power source to the circuit is stopped as necessary. The function of the semiconductor device is executed by cutting off a wiring layer constituting a fuse connected to the power supply wire by a laser light. The conventional semiconductor device will be described below.
FIG. 1 shows a semiconductor device disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-41481) (hereafter, referred to as a conventional technique 1). It is intended to easily adjust the strength of a laser light to be radiated. A field oxide film 42 is formed on a P-type semiconductor substrate 41. Moreover, a first interlayer insulating film 43 and a second interlayer insulating film 44 are formed on the field oxide film 42.
A polysilicon film 45 as a fuse element is formed on the first interlayer insulating film 43. The polysilicon film 45 is connected through contacts 48-1, 48-2 to wires 46-1, 46-2 formed of aluminum. The whole element is covered with a cover film 47. An opening 49 is formed in the cover film 47 and the second interlayer insulating film 44. The laser light is radiated to the opening 49 to cut off the polysilicon film 45.
At this time, the strength of the laser light must be finely adjusted. The reason is described below. If the radiated laser light penetrates not only the polysilicon film 45 but also the first interlayer insulating film 43 and the field oxide film 42 and further reaches the P-type semiconductor substrate 41, there may be a possibility that the polysilicon film 45 and the P-type semiconductor substrate 41 are in contact with each other.
When they are in contact with each other, if it is assumed that the wire 46-1 or 46-2 is supplied with a bias voltage Vcc and the semiconductor substrate 41 is biased to a ground potential GND, a leakage current is generated.
Thus, in this semiconductor device, an N-type diffusion layer 40 having a conductive type opposite to that of the semiconductor substrate 41 is formed in the semiconductor substrate 41 below the opening 49. According to such a configuration, even if the laser light is slightly strong, the insulation between the wires 46-1 and 46-2 and the semiconductor substrate 41 is kept unless the laser light penetrates the N-type diffusion layer 40. That is, if the polysilicon film 45 becomes in contact with the N-type diffusion layer 40, the portion between the N-type diffusion layer 40 and the semiconductor substrate 41 is in the state of PN converse junction. Hence, the leakage current does not flow.
The similar semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-211779) (hereafter, referred to as a conventional technique 2). In this device, fuses 55-1, 55-2 are provided above an N-well 56 formed in a P-type semiconductor substrate 51, as shown in FIGS. 2A and 2B. Moreover, P-type wells 50-1, 50-2 are formed to prevent these fuses 55-1, 55-2 from becoming in contact with the N-type well 56 when the fuses 55-1, 55-2 are cut off.
Incidentally, the reference number 52 denotes a field oxide film, 53 denotes an interlayer insulating film and 54 denotes a cover film. In the semiconductor device, it is not desirable that the N-type well 56 and the like are kept in floating states since the charges accumulated in the N-type well 56 may cause the potential of the P-type semiconductor substrate 51 to be changed. Hence, the N-type well 56 is biased through the contacts 57 to the bias potential Vcc.
In these conventional techniques 1 and 2, it is difficult to simultaneously achieve the improvement of the reliability to the laser light radiation and the miniaturization of the semiconductor device. In this case, the improvement of the reliability to the laser light radiation is to reduce the possibility that the leakage current flows when the fuse is in contact with the semiconductor substrate (or the well).
In the conventional technique 1, the N-type diffusion layer 40 must be deeply formed to attain the high reliability. However, when the thermomigration is performed for a long time to form deeply the diffusion layer, the diffusion layer is expanded even in a lateral direction.
The diffusion layer is usually biased to a certain potential as described in the explanation of the conventional technique 2. Typically, the diffusion layer is biased to the bias potential Vcc in the case of the N-type diffusion layer formed in the P-type semiconductor substrate, and it is biased to the ground potential GND in the case of the P-type diffusion layer formed in the N-type semiconductor substrate.
Hence, the range to implant an impurity to form the diffusion layer is determined to overlap a position of the contact of the wire to supply the bias voltage to the diffusion layer. The position of the contact is set to a position apart from the opening 49 by considering the dispersion of fragment when the laser light is radiated and the like.
If the diffusion layer is deeply formed, the diffusion layer is further expanded in the periphery from the position of the contact formed in the position apart from the opening 49. This causes the region occupied by the semiconductor device to be made larger.
In the conventional technique 2, the P-type wells 50-1, 50-2 are originally formed in the N-type well 56. Thus, the P-type wells 50-1, 50-2 can not be formed extremely deeply. To deeply form the P-type wells 50-1, 50-2, the N-type well 56 must be made deeper. If the N-type well 56 is formed deeply, the problem similar to that of the conventional technique 1 is brought about. Moreover, if the P-type wells 50-1, 50-2 are biased, the problem similar to that of the conventional technique 1 is also brought about. Furthermore, if the laser light penetrates the N-type well 56, the fuse 55 and the P-type semiconductor substrate 51 become in contact with each other and the leakage current flows.
A semiconductor device described below is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-204129). This semiconductor device is provided with a well 12 having a conductive type opposite to that of a silicon substrate 11, an insulating layer 13 formed on the well 12 and a laser trimming wiring layer 14 formed on the insulating layer 13.
However, the approach to solve the above-mentioned subjects in the present invention is not disclosed in the semiconductor device disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-204129).
Moreover, a semiconductor device described below is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-83361). This semiconductor device is provided with a semiconductor substrate having a first conductive type, a diffusion layer having a second conductive type that is opposite to the first conductive type formed in the semiconductor substrate, an insulating film formed above the diffusion layer and the semiconductor substrate, and a cutoff fuse formed on the insulating film on the diffusion layer.
However, the approach to solve the above-mentioned subjects in the present invention is not disclosed in the semiconductor device disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-83361).
The present invention is made to solve the above-described problems in the related arts as mentioned above.
The present invention is accomplished to solve the above-mentioned problem. Therefore, an object of the present invention is to provide a device for simultaneously achieving high reliability to laser light radiation and small occupation region and method of manufacturing it.
To achieve an aspect of the present invention, a semiconductor device includes a first semiconductor layer, a first well formed in a surface of the first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, a second well formed in the second semiconductor layer to be wider than the first well in a lateral direction, an insulating layer formed on the second semiconductor layer, a fuse layer formed on the insulating layer and an insulating layer formed on the fuse layer such that a part of the fuse layer is exposed.
In this case, a depth of the first well is deeper than that of the second well.
Also in this case, the fuse layer is a polysilicon film.
Further in this case, the semiconductor device further includes electrodes formed outside the exposure portion of the fuse layer.
In this case, the electrodes are connected to the second well.
Also in this case, the electrodes are connected to each other through the insulating layer to allow the first well and the second well to be biased.
In this case, the first well and the second well may be in contact with each other.
Also in this case, the first semiconductor layer and the second semiconductor layer may be formed as a single semiconductor layer.
In this case, the first and second wells have a conductive type opposite to those of the first semiconductor layer and the second semiconductor layer.
Also in this case, the first well is formed to have a first surface plane portion in the first semiconductor layer, and the exposure portion of the fuse layer is formed above the first surface plane portion.
In order to achieve another aspect of the present invention, the first well is formed to have a first surface plane portion in the first semiconductor layer, and the second well is formed to have a second surface plane portion in the second semiconductor layer, and at least a part of the first surface plane portion is formed to overlap a part of the second surface plane portion.
In order to achieve further aspect of the present invention, the first well is formed to have a first surface plane portion in the first semiconductor layer, and the second well is formed to have a second surface plane portion in the second semiconductor layer, and a whole of the first surface plane portion is formed to overlap a part of the second surface plane portion.
In order to achieve still another aspect of the present invention, the first well is formed to have a first surface plane portion in the first semiconductor layer, and the second well is formed to have a second surface plane portion in the second semiconductor layer, and a whole of the first surface plane portion is formed to substantially overlap a whole of the second surface plane portion.
In order to achieve yet still another aspect of the present invention, the second well is formed to have a second surface plane portion in the second semiconductor layer, and the second surface plane portion is formed to be externally In order to achieve another aspect of the present invention, the second well is formed to have a second surface plane portion in the second semiconductor layer, and the semiconductor device further includes electrodes formed at laterally internal portions of the second surface plane portion.
In this case, the electrodes are connected to each other through the insulating layer to allow the first well and the second well to be biased.
Also in this case, the second well is formed to have a second surface plane portion in the second semiconductor layer, and the semiconductor device further comprises a bias voltage supplying wire formed laterally outside the exposure portion of the fuse layer, and laterally inside the second surface plane portion, wherein the bias voltage supplying wire supplies a bias voltage to the first well and the second well.
In order to achieve still another aspect of the present invention, a semiconductor device includes a fuse layer, an insulating layer formed below the fuse layer, a semiconductor layer formed below the insulating layer, protecting section formed between the insulating layer and the semiconductor layer for protecting a current from flowing into the semiconductor layer, bias section for supplying a bias voltage and connecting section for connecting the bias section to the protecting section, while protecting the current from flowing into the semiconductor layer.
In this case, the protecting section and the connecting section protect a leakage current from flowing from the fuse layer to the semiconductor layer when a laser light emitted to the fuse layer penetrates the insulating layer.
Also in this case, the connecting section is formed such that a surface plane portion of the protecting section is smaller than that of the connecting section.
In order to achieve yet still another aspect of the present invention, a method of manufacturing a semiconductor device, includes the steps of selectively injecting an impurity having a first conductive type into a semiconductor substrate having a second conductive type which is opposite to the first conductive type, performing a thermomigration of the injected impurity to form a first well having the first conductive type, selectively injecting an impurity having the first conductive type into an overlapping region to form a second well shallower than the first well, at least a part of the overlapping region overlapping the first well and forming a fuse element above the second well and above the first well.
In this case, the step of selectively injecting the impurity having the first conductive type into the overlapping region includes injecting the impurity having the first conductive type into an region wider than the formed first well as the overlapping region.
Also in this case, the method of manufacturing a semiconductor device further includes the step of injecting an impurity having the second conductive type into the semiconductor substrate after the step of performing the thermomigration of the injected impurity and before the step of selectively injecting the impurity having the first conductive type into the overlapping region.
Further in this case, the method of manufacturing a semiconductor device further includes the step of forming an exposure portion of the formed fuse element above the first well.
Also in this case, the method of manufacturing a semiconductor device further includes the step of forming a bias voltage supplying wire laterally outside the first well and inside the second well to supply a bias voltage to the first well and the second well.